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1 . S3C1840
S3C1840 1 - 1 description S3C1840, a 4-bit single-chip cmos microcontroller, consists of the reliable smcs-51 cpu core with on-chip rom and ram. eight input pins and 11 output pins provide the flexibility for various i/o requirements. auto reset circuit generates reset pulse every certain period, and every halt mode termination time. the S3C1840 microcontroller has been designed for use in small system control applications that require a low-power, cost - sensitive design solution. in addition, the S3C1840 has been optimized for remote control transmitter. features rom size 1,024 bytes ram size 32 nibbles instruction set 39 instructions instruction cycle time 13.2 m sec at fxx = 455 khz input ports two 4-bit ports (24 pins)/one 4-bit port, one 2-bit ports (20 pins) output ports one 4-bit port, seven 1-bit ports (24 pins)/one 4- bit port, five1-bit ports (20 pins) built-in oscillator crystal/ceramic resonator built-in reset circuit built-in power-on reset and auto reset circuit for generating reset pulse every 131072/fxx (288 ms at fxx = 455 khz) four transmission frequencies fxx/12 (1/4 duty), fxx/12 (1/3 duty), fxx/8 (1/2 duty), and no-carrier frequency supply voltage 1.8 v-3.6 v (250 khz f osc 3.9 mhz) 2.2 v-3.6 v (3.9 mhz < f osc 6 mhz) power consumption halt mode: 1 m a (maxium) normal mode: 0.5 ma (typical) operating temperature ? 20 c to 85 c package type 24 sop, 20 dip, 20 sop oscillator frequency divide select mask option: fxx = f osc or f osc /8
S3C1840 1- 2 block diagram p1.0 - p1.3 p0.0 - p0.3 p3.0 - p3.3 6 p3 output register (pr) alu & a h 2 4 4 ram 16 x 2 x 4-bits l decoder 5 16 8 4 6 3-level stack 4 4 4 l 4 1 internal p2.9 and p2.10 4 internal p2.13 internal p2.0 p2.1 - p2.6 4 4 f xx /8 (1/2) f xx /12 (1/3) f xx /12 (1/4) no carrier internal p2.12 p2.0/rem halt div osc x i x o 4 auto reset mux pb sf pa pc 64 x 16 x 8-bits rom p2-output latch 4 figure 1-1. block diagram
S3C1840 1 - 3 pin configuration (24 sop) S3C1840 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v ss x i x o p2.6 p0.0 p0.1 p0.2 p0.3 p1.0 p1.1 p1.2 p1.3 v dd p2.0/rem test p2.1 p2.2 p2.3 p2.4 p2.5 p3.0 p3.1 p3.2 p3.3 figure 1-2. pin configuration (24 sop) table 1-1. pin description for 24 pins pin name pin number pin type description i/o circuit type p0.0-p0.3 5, 6, 7, 8 input 4-bit input port when p2.13 is low a p1.0-p1.3 9, 10, 11, 12 input 4-bit input port when p2.13 is high a p2.0 rem 23 output 1-bit individual output for remote carrier frequency (1) b p2.2-p2.5 20, 19, 18, 17 output 1-bit individual output port c p2.1, p2.6 21, 4 d p3.0-p3.3 16, 15, 14, 13 output 4-bit parallel output port c test 22 input input pin for test (normally connected to v ss ) ? x i 2 input oscillation clock input ? x o 3 output oscillation clock output ? v dd 24 ? power supply ? v ss 1 ? ground ? notes: 1. the carrier can be selected by software as fxx/12 (1/3 duty), fxx/12 (1/4 duty), fxx/8 (1/2 duty), or no-carrier frequency. 2. package type can be selected as 24 sop in the ordering sheet.
S3C1840 1- 4 pin configuration (20 dip, 20 sop) v ss x i x o p0.0 p0.1 p0.2 p0.3 p1.0 p1.1 p3.3 S3C1840 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd p2.0/rem test p2.1 p2.2 p2.3 p2.4 p3.0 p3.1 p3.2 figure 1-3. pin configuration (20 dip, 20 sop) table 1-2. pin description for 20 pins pin name pin number pin type description i/o circuit type p0.0-p0.3 4, 5, 6, 7 input 4-bit input port when p2.13 is low a p1.0-p1.1 8, 9 input 2-bit input port when p2.13 is high a p2.0/rem 19 output 1-bit individual output for remote carrier frequency (1) b p2.2-p2.4 16, 15, 14 output 1-bit individual output port c p2.1 17 d p3.0-p3.3 13, 12, 11, 10 output 4-bit parallel output port c test 18 input input pin for test (normally connected to v ss ) ? x i 2 input oscillation clock input ? x o 3 output oscillation clock output ? v dd 20 ? power supply ? v ss 1 ? ground ? notes: 1. the carrier can be selected by software as f xx/12 (1/3 duty), fxx/12 (1/4 duty), fxx/8 (1/2 duty), or no-carrier frequency. 2 package type can be selected as 20 dip, or 20 sop in the ordering sheet.
S3C1840 1 - 5 i/o circuit schematics input v dd 30 -150 k w v ss figure 1-4. i/o circuit type a v dd n-ch output data note : if data disable signal is active, halt mode, the output becomes low state. v ss data disable (note) figure 1-6. i/o circuit type c v dd output data disable (note) data note : if data disable signal is active, halt mode, the output becomes low state. v ss p-ch n-ch figure 1-5. i/o circuit type b v dd v ss n-ch data output figure 1-7. i/o circuit type d
S3C1840 1- 6 table 1-3. absolute maximum ratings parameters symbols ratings units supply voltage v dd ? 0.3 to 6 v input voltage v i ? 0.3 to v dd + 0.3 v output voltage v o ? 0.3 to v dd + 0.3 v soldering temperature t sld 260 (10 sec) c storage temperature t stg ? 55 to 125 c table 1-4. dc characteristics (v dd = 3 v, t a = 25 c) parameters symbols test conditions min typ max units supply voltage v dd 250khz f osc 3.9mhz 1.8 3.0 3.6 v 3.9mhz< f osc 6mhz 2.2 3.0 3.6 operating temperature t a ? ? 20 ? 85 c high-level input voltage v ih1 all input pins except x in 0.7 v dd ? v dd v v ih2 x in v dd -0.3 ? v dd v low-level input voltage v il1 all input pins except x in 0 ? 0.3 v dd v v il2 x in 0 ? 0.3 v high-level output current p2.0 i oh1 v o = 2.0 v ? 6.0 ? 9 ? 14 ma low-level output current p2.0 i ol1 v o = 0.4 v 1.5 3.0 4.5 ma low-level p3 output i ol2 v o = 0.4 v 0.5 1.0 2.0 ma output p2.1-p2.3 1.5 3.0 4.5 current p2.4-p2.6 0.5 1.0 2.0
S3C1840 1 - 7 table 1-4. dc characteristics (continued) (v dd = 3 v, t a = 25 c) parameters symbols test conditions min typ max units high-level input leakage current i lih1 v i = v dd ? ? 3 ua all input pins except x in i lih2 x in ? 3 10 low-level input leakage current i lil1 x in ? 0.6 ? 3 ? 10 high-level output leakage current i loh v o = v dd ? ? 3 ua all output pins except p2.0 pull-up resistance of input port r v dd = 3 v 30 70 150 k w v i = 0 v average supply current i dd v dd = 3 v ? 0.5 1.0 ma crystal/resonator non-divide option f osc = 1 mhz dvide-8 option f osc = 6 mhz halt current i ddh f osc = 0 ? ? 1.0 ua clock frequency fxx crystal/ceramic 250 ? 1000 khz oscillator frequency f osc crystal/ceramic 250 ? 1000 non-divide option crystal/ceramic 2000 6000 divide-8 option
S3C1840 1- 8 fuctional description program memory (rom) the S3C1840's program memory consists of a 1024-byte rom, organized in 16 pages. each page is 64 bytes long. (see figure 1-10). rom addressing is supported by a 10-bit register made up of two sub-registers: a 4-bit page address register (pa), and a 6-bit program counter (pc). pages 0 through 15 (fh) can each access 64 (3fh) bytes. rom addressing occurs as follows: the 10-bit register selects one of the rom's 1024-bytes. a new address is then loaded into the pc register during each instruction cycle. unless a transfer-of -control instruction such as jp,call, or ret is encountered, the pc is loaded with the next sequential 6-bit address in the page, pc + 1. in this case, the next address of 3fh would be 00h. only the page instruction can change the page buffer (pb) to a specified value. when a jp or call instruction is executed, and if the status flag is set to "1", the contents of the pb are loaded into the pa register. if the status flag is "0", however, the jp or call is executed like nop instruction in an instruction cycle and the status flag is set to "1". after that, program execution proceeds. page-in addressing all instructions, including, jp and call, can be executed by page. (see figure 1-8). when the status flag is "1", a jp or call causes a program to branch to its address (operand) in a page. pb pa pc pc address to be jumped ; if sf = 1 4 figure 1-8. page-in addressing page-to-page addressing when a page instruction occurs, and if the status flag is "1", a jp or call instruction will cause a program to branch to its address (operand) across the page (see figure 1-9). pb pa pc pb #n ; page #n pc address to be jumped ; if sf = 1 pa pb 4 note : if sf = 0 then pc pc + 1 figure 1-9. page-to-page addressing
S3C1840 1 - 9 6-bit pc 0 0 4-bit pa the 10-bit register points one of 1024 bytes at addresses 0000h to 0f3fh. after reset, it points to 0fxxh for execution in the first instruction cycle. it then becomes 0f00h in the next instruction cycle. rom address 000 03f 100 13f 200 300 23f 33f 400 43f 500 53f 600 0f00 0f3f 0fff reset address : not built-in chip page 0 page 1 page 4 page 3 page 2 page 15 page 5 figure 1-10. S3C1840 program memory map
S3C1840 1- 10 data memory (ram) the S3C1840's data memory consists of a 32-nibble ram which is organized into two files of 16 nibbles each (see figure 1-11). ram addressing is implemented by a 7-bit register, hl. it's upper 3-bit register (h) selects one of two files and its lower 4-bit register (l) selects one of 16 nibbles in the selected file. instructions which manipulate the h and l registers are as follow: select a file : mov h,#n ; h ? #n, where n must be 0,4 not h ; complement msb of h register select a nibble in a selected file : mov l,a ; l ? a mov l,a,@hl ; l ? m (h,l) mov l,#n ; l ? #n, where 0 n 0fh incs l ; l ? l + 1 decs l ; l ? l - 1 ram address 00 0f 40 4f 7f file 4 file 0 : not built-in chip 3-bit 4-bit l the 7-bit hl register pair points to one of the 32 nibbles. h register selects one of two files; 0, 4 l register selects one of 16 nibbles; 0 to 0fh after reset, the hl register pair becomes to unknown state. h figure 1-11. S3C1840 data memory map
S3C1840 1 - 11 register descriptions stack register (sr) three levels of subroutine nesting are supported by a three-level stack as shown in figure 1-12. each subroutine call (call) pushes the next pa and pc address into the stack. the latest stack to be stored will be overwritten and lost. each return instruction (ret) pops the stack back into the pa and pc registers. pa pc sr : push operation (call) : pop operation (ret) figure 1-12. stack operations page address register (pa), page buffer register (pb) the page address register (pa) and page buffer register (pb) are 4-bit registers. the pa always specifies the current page. a page select instruction (page #n) loads the value "n" into the pb. when jp or call instruction is executed, and if the status flag (sf) is set to 1, the contents of pb are loaded into pa. if sf is "0", however, the jp or call is executed like nop instruction and sf is set to "1". the contents of pb don't be loaded. figure 1-13 illustrates this concept. page #n ; pb n pb pa 4 4 jp xxx (call xxx) ; pa pb common bus if sf = 1 figure 1-13. pa, pb operations
S3C1840 1- 12 arithmetic logic unit (alu), accumulator (a) the smcs-51 cpu contains an alu and its own 4-bit register (accumulator) which is the source and destination register for most i/o, arithmetic, logic, and data memory access operations. arithmetic functions and logical operations will set the status flag (sf) to "0" or "1". status latch (sl) the status latch (sl) flag is an 1-bit flip-flop register. only the "cpne l,a" instruction can change the value of sl. if the result of a "cpne l,a" instruction is true, the sl is set to "1"; if not true, to "0". status flag : sf the status flag (sf) is a 1-bit flip-flop register which enables programs to conditionally skip an instruction. all instructions, including jp and call, are executed when sf is "1". but if sf is "0", the program executes nop instruction instead of jp or call and resets sf to "1". then, program execution proceeds. the following instructions set the sf to "0": arithm etic instructions adds a, #n ; if no carry adds a,@hl ; if no carry incs a,2hl ; if no carry incs a ; if no carry incs l ; if no carry subs a,@hl ; if no carry decs a,@hl ; if no carry decs a ; if no carry decs l ; if no carry compare instructions cpne @hl,a ; if m(h,l) = (a) cpnz @hl ; if m(h,l) = 0 cpne l,#n ; if (l) = # cpne l,a ; if (l) = (a) cpne a,@hl ; if (a) > m(h,l) cpnz p0 ; if (p0) = 0 cpbt @hl,b ; if m (h,l,b) 1 1 data transfer instructions mov @hl+,a ; if no carry mov @hl_,a ; if borrow logical instructions noti a ; if (a) 1 0 after operation
S3C1840 1 - 13 input ports : p0, p1 the p0 and p1 input ports have internal pull-up 30-150 k w resistors, (see i/o circuit type a), each multiplexed to a common bus (see figure 1-14). if the p2.13 pin is programmed to low, then port 0 is selected as the input port. otherwise, if the p2.13 pin high, port 1 is selected. common bus mux p0.0-p0.3 4 p2.13 (internal) p1.0-p1.3 4 figure 1-14. S3C1840 input port output ports : p2, p3 the p2 and p3 output ports can be configured as push-pull (p2.0/rem only) and open drain (p2.1-p2.6, p3.0- p3.3) as follows: standard push-pull : a cmos push-pull buffer with n-channel transistor to ground in conjunction with a p- channel transistor to v dd , compatible with cmos and ttl. (see i/o circuit type b). n-channel open drain : an n-channel transistor to ground, compatible with cmos and ttl. (see i/o circuit type c and d). p2.0, p2.2-p2.5 and p3.0-p3.3 pins become low state in halt mode. the l register specifies p2 output pins (p2.0/rem-p2.6, p2.9-p2.10, p2.12, and p2.13) individually as follows: setb p2.(l) : set port 2 bits to correspond to l-register contents. clrb p2.(l) : clear port 2 bits to correspond to l-register contents. p3 output pins p3.0-p3.3 are parallel output pins. for the S3C1840, only the 4-bit accumulator outputs its value to the p3 port by the output instruction "out p3, @sl+ a" (the value of the status latch (sl) does not matter).
S3C1840 1- 14 transmission carrier frequency one of four carrier frequencies can be selected and transmitted through the p2.0/rem pin by programming the internal p2.9, p2.10 and p2.0 pins (see table 1-5). figure 1-16 shows a simplified diagram of the various transmission circuits. table 1-5. carrier frequency selection table p2.10 p2.9 carrier frequency of p2.0/rem pin 0 0 fxx/12, 1/3 duty 0 1 fxx/8, 1/2 duty 1 0 fxx/12, 1/4 duty 1 1 no carrier
S3C1840 1 - 15 4 x 1 mux internal p2.9 f xx /8, 1/2 duty f xx /12, 1/3 duty f xx /12, 1/4 duty v dd (no carry) internal p2.10 internal p2.0 p2.0/rem system clock frequency internal p2.0 p2.0/rem (f xx /12, 1/3 duty) p2.0/rem (f xx /8, 1/2 duty) p2.0/rem (no carry) p2.0/rem (f xx /12, 1/4 duty) figure 1-15. diagram of transmission circuits
S3C1840 1- 16 halt mode the halt mode is used to reduce power consumption by stopping the clock and holding the states of all internal operations fixed. this mode is very useful in battery-powered instruments. it also holds the controller in wait status for external stimulus to start some event. the S3C1840 can be halted by programming the p2.12 pin high, and by forcing p0 input pins (p0.0-p0.3) to high and p1 input pins (p1.0-p1.3) to high, concurrently (see figure 1-16). when in halt mode, the internal circuitry does not receive any clock signal, and all p2, p3 output pins become low states. however, p2.1 and p2.6 pins retain their programmed values until the device is re-started as follows: forcing any p0 and p1 input pins to low : system reset occurs and it continues to operate from the reset address. an oscillation stabilization time of 13 msec in fxx = 455 khz crystal oscillation is needed for stability (see figure 1-17). p0.3-p0.0 p1.3-p1.0 v dd 4 internal p2.12 internal halt system reset 4 figure 1-16. block diagram of halt logic normal mode halt mode halt mode x'tal 13 msec (minimum) 120 m sec (typical) halt figure 1-17. release timing for halt or reset to normal mode in crystal oscillation
S3C1840 1 - 17 reset all reset operations are internal in the S3C1840. it has an internal power-on reset circuit consisting of a 7 pf capacitor and a 1 m w resistor (see figure 1-18). the controller also contains an auto-reset circuit that resets the chip every 131,072 oscillator clock cycles (288 ms at a fxx = 455 khz clock frequency). the auto-reset counter is cleared by the rising edge of a internal p2.0 pin, by halt, or by the power-on reset pulse (see figure 1-19). therefore, no clocks are sent to the counter and the time-out is suspended in halt mode. when a reset occurs during program execution, a transient condition occurs. the pa register is immediately initialized to 0fh. the pc, however, is not reset to 0h until one instruction cycle later. for example, if pc is 1ah when a reset pulse is generated, the instruction at 0f1ah is executed, followed by the instruction at 0f00h. after a reset, approximately 13 msec is needed before program execution proceeds (assuming fxx = 455 khz ceramic oscillation). upon initialization, registers are set as follows: pc register to 0 in next instruction cycle pa and pb registers to 0fh (15th page) sf and sl registers to 1 hl registers to unknown state all internal/external output pins (p3.0-p3.3, p2.0/rem-p2.6, p2.9, p2.10, p2.12 and p2.13) to low. 1 m w v dd v ss S3C1840 7 pf figure 1-18. S3C1840's power-on reset circuit
S3C1840 1- 18 system reset internal halt the auto-reset counter is cleared every 131,072/fxx (288 msec if fxx is 455 khz). power-on reset auto-reset counter internal halt internal p2.0 fxx clk clr figure 1-19. auto reset block diagram osc divide option circuit the osc divide option circuit provides a maximum 1mhz fxx system clock. f osc which is generated in oscillation circuit is divided eight or non-divide in this circuit to produce fxx. this dividing ratio will be chosen by mask option. (see figure 1-20) f osc : oscillator clock fxx : system clock (f osc or f osc /8) f cpu : cpu clock (f cpu = fxx/6) 1 instruction cycle clock x i x o f osc mask option osc divide-8 f xx figure 1-20. S3C1840 osc divide option circuit
S3C1840 1 - 19 package dimensions note : dimensions are in millimeters. 24-sop-375 10.30 0 .30 #13 #24 #1 #12 15.74 max 15.34 0 .20 (0.69) 0-8 0.15 + 0.10 - 0.05 9.53 7.50 0.20 0.85 0.20 0.05 min 2.30 0.10 2.50 max 0.38 0.10 max + 0.10 - 0.05 1.27 figure 1-21. 24-sop-375
S3C1840 1- 20 note : dimensions are in millimeters. 20-sop-375 10.30 0 .30 #11 #20 #1 #10 13.14 max 12.74 0 .20 (0.66) 0-8 0.203 + 0.10 - 0.05 9.53 7.50 0.20 0.85 0.20 0.05 min 2.30 0.10 2.50 max 0.40 0.10 max + 0.10 - 0.05 1.27 figure 1-22. 20-sop-375
S3C1840 1 - 21 note : dimensions are in millimeters. 20-sop-300 7.80 0 .30 #11 #20 #1 #10 14.10 max 13.70 0 .20 (1.14) 0-8 0.20 + 0.10 - 0.05 7.62 5.40 0.20 0.60 0.20 0.05 min 1.70 0.10 2.00 max 0.40 0.10 max + 0.10 - 0.05 1.27 figure 1-23. 20-sop-300
S3C1840 1- 22 note : dimensions are in millimeters. 26.80 max 26.40 0 .20 (1.77) 20-dip-300a 6.40 0 .20 #20 #1 0.46 0.10 1.52 0.10 #11 #10 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max figure 1-24. 20-dip-300a
5. instruction set
S3C1840/c1850/c1860/p1860 instruction set 5 - 1 instruction set description abbreviations and symbols table specifies internal architecture, instruction operand and operational symbols. as mentioned before, jp and call instructions are executed normally only when sf is high. if sf is low, the program executes nop instruction instead of them and sets sf to high. and then, the program executes a next instruction. in addition, jpl and call are long jump and long call instructions which consists of page and jp/call instructions. table 5-1. abbreviations and symbols symbol description symbol description l l register (4 bits) sf status flag a accumulator (4 bits) p3 p4-output (l) the contents of the l register p0 p0 input (4 bits) (a) the contents of the accumulator d any binary number sl status latch (1 bit) dst destination operand pb page buffer register (4 bits) c carry flag pa page address register (4bits) src source operand p2 p2-output reg register pc program counter ? transfer sr stack register + addition or increment by 1 h h register equal or less than m ram addressed by h and l registers ( ) the complement of the contents (h) the contents of the h register @ indirect register address prefix m (h,l) the contents of the ram addressed by h,l #n constant n (immediate 3or 4-bit data) b bit address of the ram [(h,l)] addressed by h,l ? is exchanged with 1 not equal to - subtract or decrement by 1
instruction set S3C1840/c1850/c1860/p1860 5 - 2 table 5-2. instruction set summary mnemonic operand description mov instructions mov mov mov mov mov mov mov mov mov mov movz xch page l,a a,l @hl,a a,@hl l,@hl @hl+,a @hl-,a l,#n h,#n @hl+,#n @hl,a @hl,a #n move a to register l move l register to a move a to indirect data memory move indirect data memory to a move indirect data memory to register l move a to indirect data memory and increment register l move a to indirect data memory and decrement register l move immediate data to register l move immediate data to register h move immediate data to indirect data memory and increment register l move a to indirect data memory and clear a exchange a with indirect data memory set pb register to n program control instructions cpne cpnz cpne cpne cple cpnz cpbt jp call ret @hl,a @hl l,a l,#n a,@hl p0 @hl,b dst dst compare a to indirect data memory and set sf if not equal set sf if indirect data memory compare a to register l, set sf and sl if not equal compare immediate data to register l and set sf if not equal set sf if a is less than or equal to indirect data memory set sf if a is less than or equal to indirect data memory test indirect data memory bit and set sf if indirect bit is one jump if sf flag is set call subroutine if sf is set return from subroutine i/o instructions setb clrb in out p2.(l) p2.(l) a,p0 p3,@sl+a set bit clear bit input p0 to a output a to p4-pla output port logical instructions noti not clr a h a complement a and increment a complement msb of h register clear arithmetic instructions adds adds subs incs incs incs decs decs decs a,@hl a,#n a,@hl a,@hl l a a a,@hl l add indirect data memory to a add immediate data to a subtract a from indirect data memory increment indirect data memory and load the result in a increment register l increment a decrement a decrement indirect data memory and load the result in a decrement register l bit manipulation instruction setb clrb @hl.b @hl.b set indirect data memory bit clear indirect data memory bit
S3C1840/c1850/c1860/p1860 instruction set 5 - 3 lower nibble (hex) upper nibble (hex) cpne @hl,a cple a,@hl cpne l,a xch @hl,a decs l incs l adds a,@hl decs a,@hl in a,p0 not h out p3,@sl+a clrb p2.(l) setb p2.(l) cpnz p0 ret page #n mov l,a mov a,@hl mov l,@hl mov a,l mov @hl-,a mov @hl+,a movz @hl,a mov @hl,a mov h,#n setb @hl.b clrb @hl.b cpbt @hl.b mov l,#n mov @hl+#n incs a jp jp jp jp call call call call cpne l,#n subs a,@hl noti a incs a,@hl cpnz @hl adds a,#n decs a adds a,#n clr a 0 1 3 4 5 6 2 8 9 a b c d e f 7 0 1 3 4 5 6 2 8 9 a b c d e f 7 figure5-1. ks51 opcode map
instruction set S3C1840/c1850/c1860/p1860 5 - 4 mov l,a binary code: 0 0 1 0 0 0 0 0 description: the contents of the accumulator are moved to register l. the contents of the source operand are not affected. operation: (l) ? (a) flags: sf : set to one sl : unaffected example: clr a ; clear the contents of a mov l,a ; move 0h to reg l mov a,l binary code: 0 0 1 0 0 0 1 1 description: the contents of register l are moved to the accumulator. the contents of the source operand are not affected. operation: (a) ? (l) flags: sf : set to one sl : unaffected example: mov l,#3h ; move 3h to reg l mov a,l ; move 0h to a mov @hl,a binary code: 0 0 1 0 0 1 1 1 description: the contents of the accumulator are moved to the data memory whose address is specified by registers h and l. the contents of the source operand are not affected. operation: m [(h,l)] ? (a) flags: sf : set to one sl : unaffected example: clr a ; clear the contents of a mov h,#0h ; move 0h to reg h mov l,#3h ; move 3h to reg l mov @hl,a ; move 0h to ram address 03h
S3C1840/c1850/c1860/p1860 instruction set 5 - 5 mov a,@hl binary code: 0 0 1 0 0 0 0 1 description: the contents of the data memory addressed by registers h and l are moved to accumulator. the contents of the source operand are not affected. operation: (a) ? m [(h,l)] flags: sf : set to one sl : unaffected example: assume hl contains 04h mov a,@hl ; move contents of ram addressed 04h to a mov l,@hl binary code: 0 0 1 0 0 0 1 0 description: the contents of the data memory addressed by registers h and l are moved to register l. the contents of the source operand are not affected. operation: (l) ? m [(h,l)] flags: sf : set to one sl : unaffected example: assume hl contains 04h mov l,@hl ; move contents of ram address 4h to reg l cpne l,#5h ; compare 5h to reg l values jp xx ; jump to xx if reg l value is not 5h jp yy ; jump to yy if reg l value is 5h mov @hl+,a binary code: 0 0 1 0 0 1 0 1 description: the contents of the accumulator are moved to the data memory addressed by registers h,l; l register contents are incremented by one. the contents of the source operand are not affected. operation: m [(h,l)] ? (a), l ? l + 1 flags: sf : set if carry occurs; cleared otherwise sl : unaffected example: mov h,#0h mov l,#0fh clr a mov @hl+a ; move 0h to ram address 0fh and increment reg l value by one jp prt ; jump to prt, since there is a carry from increment
instruction set S3C1840/c1850/c1860/p1860 5 - 6 mov @hl-a binary code: 0 0 1 0 0 1 0 0 description: the contents of accumulator are moved to the data memory addressed by registers h,l; l register contents are decremented by one. the contents of the source operand are not affected. operation: m [(h,l)] ? (a), l ? l - 1 flags: sf : set if no borrow; cleared otherwise sl : unaffected example: mov h,#0h mov l,#3h clr a mov @hl-,a jp abc mov l,#n binary code: 0 1 0 0 d d d d description: the 4-bit value specified by n (data) is loaded into register l. the contents of the source operand are not affected. operation: (l) ? #n flags: sf : set to one sl : unaffected example: mov l,#8h ; 8h is moved to reg l mov h,#n binary code: 0 0 1 0 1 d d d description: the 3-bit value specified by n (data) is moved to register h. the contents of the source operand are not affected. operation: (h) ? #n flags: sf : set to one sl : unaffected example: mov h,#4h ; 4h is moved into reg h
S3C1840/c1850/c1860/p1860 instruction set 5 - 7 mov @hl+,#n binary code: 0 1 1 0 d d d d description: the 4-bit value specified by n (data) is moved to data memory addressed by registers h,l; l register contents are incremented by one. the contents of the source operand are not affected. operation: m [(h,l)] ? #n, l ? l + 1 flags: sf : set to one sl : unaffected example: mov h,#0h mov l,#7h mov @hl+,#9h ; move 9h to ram address 07h and increment reg l value by one, then reg l contains 8h movz @hl,a binary code: 0 0 1 0 0 1 1 0 description: the contents of the accumulator are moved to the data memory addressed by registers h,l; accumulator contents are cleared to zero. operation: m [(h,l)] ? (a), (a) ? 0 flags: sf : set to one sl : unaffected example: mov l,#3h mov a,l movz @hl,a ; move 3h to indirect ram and clear a to zero mov l,a ; move 0h to reg l setb p2.(l) ; set p2.0 to 1 xch @hl,a binary code: 0 0 0 0 0 0 1 1 description: this instruction exchanges the contents of the data memory addressed by registers h and l with the accumulator contents. operation: m [(h,l)] ? (a) flags: sf : set to one sl : unaffected example: mov h,#0h mov l,#6h clr a ; clear a to zero adds a,#5h ; add 5h to a xch @hl,a ; exchange 5h with contents of ram address 06h
instruction set S3C1840/c1850/c1860/p1860 5 - 8 page #n binary code: 0 0 0 1 d d d d description: the immediate 4-bit value specified by n (data) is loaded into the pb register. operation: (pb) ? #n flags: sf : set to one sl : unaffected example: page #3h ; move 3h to page buffer jp an ; jump to label an located at page 3 if sf is one; otherwise, it is skipped cpne @hl,a binary code: 0 0 0 0 0 0 0 0 description: the contents of accumulator are compared to the contents of indirect data memory; an appropriate flag is set if their values are not equal. the contents of both operands are unaffected by the comparison. operation: m [(h,l)] 1 (a) flags: sf : set if not equal, cleared otherwise sl : unaffected example: clr a adds a,#3h mov h,#0h mov l,#6h cpne @hl,a ; acc value 3h is compared to contents of ram address 06h jp oa ; jump to oa if values of ram address 06h are not 3h jp ob ; jump to ob if values of ram address 06h are 3h
S3C1840/c1850/c1860/p1860 instruction set 5 - 9 cpnz @hl binary code: 0 0 1 1 1 1 1 1 description: this instruction compares the magnitude of indirect data memory with zero, and the appropriate flag is set if their values are not equal, i.e., if the contents of indirect data memory are not zero. the contents of operand are unaffected by the comparison. operation: m [(h,l)] 1 0 flags: sf : set if not zero, cleared otherwise sl : unaffected example: assume the contents of ram address are 4h cpnz @hl ; compare 4h with zero jp eq ; jump to eq because the result is not equal jp wait cpne l,a binary code: 0 0 0 0 0 0 1 0 description: the contents of the accumulator are compared to the contents of register l; the appropriate flags are set if their values are not equal. the contents of both operands are unaffected by the comparison. operation: (l) 1 (a) flags: sf : set if not equal, cleared otherwise sl : set if not equal, cleared otherwise example: assume reg l contains 5h, a contains 4h cpne l,a ; compare a to reg l values jp k1 ; jump to k1 because the result is not equal jp k2
instruction set S3C1840/c1850/c1860/p1860 5 - 10 cpne l,#n binary code: 0 1 0 1 d d d d description: this instruction compare the immediate 4 bit data n with the contents of register l, and sets an appropriate flag if their values are not equal. the contents of both operands are unaffected by the comparison. operation: (l) 1 #n flags: sf : set if not equal, cleared otherwise sl : unaffected example: clr a adds a,#4h mov l,a cpne l,#5h ; compare immediate data 5h to reg l values jp k3 ; jump to k3 because the result is not equal cpne a,@hl binary code: 0 0 0 0 0 0 0 1 description: the contents of indirect data memory are compared to the contents of the accumulator. appropriate flags are set if the contents of the accumulator are less than or equal to the contents of indirect data memory. the contents of both operands are unaffected by the comparison. operation: (a) m [(h,l)] flags: sf : set if less than or equal to, cleared otherwise sl : unaffected example: assume ram address holds 8h cple a,@hl ; compare 8h to a values jp mar ; jump to mar if 0h a 8h jp bpr ; jump to bpr if 9h a 0fh
S3C1840/c1850/c1860/p1860 instruction set 5 - 11 cpnz p0 binary code: 0 0 0 0 1 1 1 0 description: the instruction compares the contents of port 0 with zero. appropriate flags are set if their values are not equal, i.e., if the contents of port 0 are not zero. the contents of the operand are unaffected by the comparison. operation: (p0) 1 0 flags: sf : set if not zero, cleared otherwise sl : unaffected example: mov l,#0dh clrb p2.(l) ; clear p2.13, i.e., select p0 input cpnz p0 ; compare p0 to zero jp keyin ; jump to keyin if p0 1 0 jp nokey ; jump to nokey if p0 = 0 cpbt @hl,b binary code: 0 0 1 1 1 0 d d description: cpbt tests indirect data memory bit and sets appropriate flags if the bit value is one. the contents of operand are unaffected by the test. operation: m [(h,l)] = 1 flags: sf : set if one, cleared otherwise sl : unaffected example: mov h,#0h mov l,#0bh cpbt @hl,3 ; test ram address 0bh bit 3 jp q1 ; jump to q1 if ram address bit 3 is 1 jp q2 ; jump to q2 if ram address bit 3 is 0
instruction set S3C1840/c1850/c1860/p1860 5 - 12 jp dst binary code: 1 0 d d d d d d description: the jp transfers program control to the destination address if the sf is one. the conditional jump replaces the contents of the program counter with the address indicated and transfers control to that location. had the sf flag not been set, control would have proceeded with the next instruction. operation: if sf = 1 ; pc ? (w), pa ? pb flags: sf : set to one sl : unaffected example: jp sutin1 ; this instruction will cause program execution to branch to the instruction at label sutin; sutin1 must be within the current page call dst binary code: 1 1 d d d d d d description: if the sf flag is set to 1, this instruction calls a subroutine located at the indicated address, and then pushes the current contents of the program counter to the top of the stack. the program counter value used is the address of the first instruction following the call ins. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure, the return (ret) instruction can be used to return to the original program flow. operation: if sf = 1 ; sri ? pc + 1, psri ? pa pc ? i (w), pa ? pb flags: sf : set to one sl : unaffected example: call acd1 ; call subroutine located at the label acd1 where acd1 must be within the current page ret binary code: 0 0 0 0 1 1 1 1 description: this instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement executed is that addressed by the new contents of the program counter. operation: pc ? sri, pb ? psri pa ? pb flags: sf : set to one sl : unaffected example: ret ; return from subroutine
S3C1840/c1850/c1860/p1860 instruction set 5 - 13 setb p2.(l) binary code: 0 0 0 0 1 1 0 1 description: this instruction sets the port 2 bit addressed by register l without affecting any other bits in the destination. operation: p2.(l) ? 1 flags: sf : set to one sl : unaffected example: mov l,#0h setb p2.(l) ; set p2.0 to 1 clrb p2.(l) binary code: 0 0 0 0 1 1 0 0 description: this instruction clears the port 2 bit addressed by register l without affecting any other bits in the destination. operation: p2.(l) ? 0 flags: sf : set to one sl : unaffected example: mov l,#0h clrb p2.(l) ; clear p2.0 to 0 in a,p0 binary code: 0 0 0 0 1 0 0 0 description: data present on port n is transferred (read) to the accumulator. operation: (a) ? (pn) (n = 0,1) flags: sf : set to one sl : unaffected example: in a,p0 ; input port 0 data to acc mov l,a cpne l,#3h jp ox ; jump to ox if port 0 data 1 3h jp qp ; jump to qp if port 0 data = 3h
instruction set S3C1840/c1850/c1860/p1860 5 - 14 out p3,@sl+a binary code: 0 0 0 0 1 0 1 0 description: the contents of the accumulator and sl are transferred to the p3 output register. operation: (p3 output register) ? (a) + (sl) flags: sf : set to one sl : unaffected example: clr a out p3,@sl+a ; zero output on port 3 noti a binary code: 0 0 1 1 1 1 0 1 description: the contents of the accumulator are complemented; all 1 bits are changed to 0, and vice- versa, and then incremented by one. operation: (a) ? (a), (a) ? (a) +1 flags: sf : set if the result is zero, cleared otherwise sl : unaffected example: clr a adds a,#7h noti a ; complement 7h (0111b) and increment the result by one; the instruction noti a then leaves 9h (1001b) in a
S3C1840/c1850/c1860/p1860 instruction set 5 - 15 not h binary code: 0 0 0 0 1 0 0 1 description: the msb of register h is complemented, operation: (h) ? (h) flags: sf : set to one sl : unaffected example: mov h,#4h not h ; complement 4h (100b), then it leaves 00h (000b) in reg h clr a binary code: 0 1 1 1 1 1 1 1 description: the contents of the accumulator are cleared to zero (all bits set on zero). operation: (a) ? 0 flags: sf : set to one sl : unaffected example: clr a ; a value are cleared to zero adds a,@hl binary code: 0 0 0 0 0 1 1 0 description: adds adds the contents of indirect data memory to accumulator, leaving the result in the accumulator. the contents of the source operand are unaffected. operation: (a) ? m [(h,l)] + (a) flags: sf : set if a carry occurred, cleared otherwise sl : unaffected example: assume ram address holds 5h clr a ; clear a to zero adds a,@hl ; this instruction will leaves 5h in a
instruction set S3C1840/c1850/c1860/p1860 5 - 16 adds a,#n binary code: 0 1 1 1 d d d d description: the specified 4-bit data n is added to the accumulator and the sum is stored in the accumulator. operation: (a) ? (a) + #n flags: sf : set if a carry occurred, cleared otherwise sl : unaffected example: clr a ; clear a to zero adds a,#4h ; add 4h to a, it leaves 4h in a subs a,@hl binary code: 0 0 1 1 1 1 0 0 description: subs subtracts the contents of accumulator from the contents of indirect data memory, leaving the result in the accumulator. the contents of source operand are unaffected. operation: (a) ? m [(h,l)] - (a) flags: sf : set if no borrow occurred, cleared otherwise sl : unaffected example: assume ram address holds 0ch mov l,#8h mov a,l subs a,@hl ; subtract a from 0ch; it will leave 4h in a incs a,@hl binary code: 0 0 1 1 1 1 1 0 description: the contents of indirect data memory are incremented by one and the result is loaded into the accumulator. the contents of indirect data memory are unaffected. operation: (a) ? m [(h,l)] + 1 flags: sf : set if a carry occurred, cleared otherwise sl : unaffected example: assume ram address holds 6h clr a ; clear a to zero incs a,@hl ; increment 6h by one and leave 7h in a
S3C1840/c1850/c1860/p1860 instruction set 5 - 17 incs l binary code: 0 0 0 0 0 1 0 1 description: the contents of the l register are incremented by one. operation: (l) ? (l) + 1 flags: sf : set if a carry occurred, cleared otherwise sl : unaffected example: mov l,#5h incs l ; increment reg l value 5h by one incs a binary code: 0 1 1 1 0 0 0 0 description: the contents of the accumulator are incremented by one. operation: (a) ? (a) + 1 flags: sf : set if no borrow occurred, cleared otherwise sl : unaffected example: mov l,#5h mov a,l incs a ; increment 5h by one decs a binary code: 0 1 1 1 0 1 1 1 description: the contents of the accumulator are decremented by one. operation: (a) ? (a) - 1 flags: sf : set if a carry occurred, cleared otherwise sl : unaffected example: mov l,#0bh mov a,l decs a ; the instruction leaves the value 0ah in a
instruction set S3C1840/c1850/c1860/p1860 5 - 18 decs a,@hl binary code: 0 0 0 0 0 1 1 1 description: the contents of the data memory addressed by the h and l registers are decremented by one and the result is loaded in the accumulator. but the contents of data memory are not affected. operation: (a) ? m [(h,l)] - 1 flags: sf : set if a carry occurred, cleared otherwise sl : unaffected example: assume ram address holds 5h mov l,#0ah mov a,l decs a,@hl ; decrement the value 5h by one, and the result value 4h is loaded in a decs l binary code: 0 0 0 0 0 1 0 0 description: the contents of the l register are decremented by one. operation: (l) ? (l) - 1 flags: sf : set if no borrow occurred, cleared otherwise sl : unaffected example: mov l,#3h decs l ; this instruction leaves the value 2h in reg l setb @hl,b binary code: 0 0 1 1 0 0 d d description: this instruction sets indirect data memory bit addressed by registers h and l without affecting any other bits in the destination. operation: b ? 1 (b = 0,1,2,3) flags: sf : set to one sl : unaffected example: mov h,#0h mov l,#5h setb @hl.2 ; set ram address 05h bit 2 to 1
S3C1840/c1850/c1860/p1860 instruction set 5 - 19 decs a,@hl binary code: 0 0 1 1 0 1 d d description: this instruction clears the indirect data memory bit addressed by registers h and l without affecting any other bits in the destination. operation: b ? 1 (b = 0,1,2,3) flags: sf : set to one sl : unaffected example: mov h,#0h mov l,#5h clrb @hl.3 ; clear ram address 05h bit 3 to zero
6. development tools

S3C1840/c1850/c1860/p1860 development t ools 6- 1 smds the samsung microcontroller development system, smds is a complete pc-based development environment for S3C1840/c1850/c1860 microcontroller. the smds is powerful, reliable, and portable. the smds tool set includes a versatile debugging utility, trace with built-in logic analyzer, and performance measurement applications. its window-oriented program development structure makes smds easy to use. smds has three components: ? ibm pc- compatible smds software, all device-specific development files, and the sama assembler. ? development system kit including main board, personality board, smds manual, and target board adapter, if required. ? device-specific target board. smds product versions as of the date of this publication, two versions of the smds are being supported: ? smds version 4.8 (s/w) and smds version 3.6 (h/w); last release: january, 1994. ? smds2 version 5.3 (s/w) and smds2 version 1.3 (h/w); last release: november, 1995. the new smds2 version 1.3 is intended to replace the older version 3.6 smds. the smds2 contains many enhancements to both hardware and software. these development systems are also supported by the personality boards of samsung's microcontroller series: s3c1, s3c7, and s3c8. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. compiled program code includes the object code that is used for rom data and required smds program control data. to compile programs, sama requires a source file and an auxiliary definition (def) file with device-specific information. target boards and piggybacks target boards are available for S3C1840/c1850/c1860 microcontroller. all required target system cables and adapters are included with the device-specific target board. piggyback chips are provided to customers in limited quantities for S3C1840/c1850 microcontroller. the S3C1840/c1850 piggyback chips, pb51840-20 and pb51840/51850-24 are now available.
development tools s 3c1840/c1850/c1860/p1860 6- 2 pb51840-20 is 20 dip piggyback chip for 20 dip, 20 sop package device of S3C1840 microcontroller. pb51840/51850-24 is 24dip piggyback chip for 24 sop package device of S3C1840/c1850 microcontroller. ibm-pc or compatiable internal bus 5-volt power supply main board personality board front panel board rs-232c smds2 pod target board target application system target cable figure 6-1. smds product configuration (smds2)
S3C1840/c1850/c1860/p1860 development t ools 6- 3 tb51840/51850a target board the tb51840/51850a target board is used for the S3C1840/c1850/c1860 microcontroller. it is supported by the smds2 development system only. 25 tb51840/51850a/51860 sm1243a 1 cn1 to user_vcc off on reset 1 u5 u4 gnd v cc u5 u6 1 64 64 sdip ks51899 eva chip u1 32 33 j102 j101 p2 off on ra3 ra1 ra2 + + + p2.6 p2.5 p2.4 + + + + p2.3 p2.2 p2.1 p2.0 figure 6-2. tb51840/51850a target board configuration
development tools s 3c1840/c1850/c1860/p1860 6- 4 table 6-1. power selection settings for tb51840/51950a 'to user_vcc' settings operating mode comments to user_vcc on off target system smds2 tb51840/ 51850a v cc v ss v cc the smds2 supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off target system smds2 tb51840/ 51850a v cc v ss v cc external the smds2 supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. led 2.0-led 2.6: these leds are used to display value of the p2.0-p2.6. it will be turn on, if the value is low. p2 option switch: switch on: you can see the port value using the led display. switch off: you can't see the port value. that is, the led won't be turn on by the port value.
S3C1840/c1850/c1860/p1860 development t ools 6- 5 24 23 22 21 20 19 18 17 16 15 j101 24-dip socket 2 3 4 5 6 7 8 9 1 14 13 10 11 12 v ss x in x out p2.6 p0.0 p0.1 p0.2 p0.3 p1.0 p1.2 p1.3 p1.1 v ss x in x out p0.0 p0.1 p0.2 p0.3 p1.0 p1.2 p1.3 p1.1 p2.6 figure 6-3. 24 dip socket for tb51840/51850a (S3C1840/c1850, 24 sop) target board 24-dip socket target system j101 target cable for 24 dip package part name: as24d order code: sm6303 1 24 12 13 1 24 12 13 figure 6-4. tb51840/51850a cable for 24 dip package
development tools s 3c1840/c1850/c1860/p1860 6- 6 j102 p0.0 p0.1 p0.2 p0.3 p1.0 p1.1 p3.3 p2.2 p2.3 p2.4 p3.0 p3.1 p3.2 p2.1 20-dip socket v ss x in x out v dd p2.0/rem test 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 6-5. 20 dip socket for tb51840a (S3C1840/c1860, 20 dip, 20 sop) target board 20-dip socket target system j101 target cable for 20 dip package part name: as20d order code: sm6304 1 20 10 11 1 20 10 11 figure 6-6. tb51840a cable for 20 dip package
7. remote control tx. application note

S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 1 description of the S3C1840/c1850/c1860 mcus the S3C1840/c1850/c1860 4-bit single-chip cmos microcontroller is designed using the reliable smcs-51 cpu core with on-chip rom and ram. an auto-reset circuit generates a reset pulse in regular intervals, and can be used to initiate a halt mode release. the S3C1840/c1850/c1860 microcontroller is intended for use in small system control applications that require a low-power and cost-sensitive design solution. in addition, the S3C1840/c1850/c1860 has been optimized for remote control transmitters. features table 7-1. S3C1840/c1850/c1860 features feature S3C1840 s3c1850 s3c1860 rom 1024 bytes 1024 bytes 1024 bytes ram 32 x 4 bits 32 x 4 bits 32 x 4 bits carrier frequency fxx/12, fxx/8, no carrier fxx/12, fxx/8, no carrier fxx/12, fxx/8, no carrier operating voltage 250 khz f osc 3.9 mhz 1.8 v to 3.6 v, 3.9 mhz < f osc < 6 mhz 2.2 v to 3.6 v 250 khz f osc 3.9mhz 1.8 v to 3.6 v, 3.9 mhz < f osc < 6 mhz 2.2 v to 3.6 v 250 khz f osc 3.9 mhz 1.8 v to 3.6 v, 3.9 mhz < f osc < 6 mhz 2.2 v to 3.6 v low-level output current p2.0 (iol1) typ. 3.0ma (at vo=0.4v) typ. 210ma (at vo=0.4v) typ. 280ma (at vo=0.4v) typ. 260ma (at vo=0.5v) typ. 320ma (at vo=0.5v) package 24 sop, 20 sop/dip 24 sop 20 sop/dip piggyback o o x otp x x o (s3p1860:divide-8 only) tr. for i.r.led drive x built-in built-in power on reset circuit built-in built-in x oscillation start and reset circuit (osr) x x built-in table 7-2. S3C1840/c1850/c1860 package types (note) item 24 pins 20 pins package 24 sop-375 20 dip-300a 20 sop-300 20 sop-375 note : the s3c1850 has 24 pin package type only and s3c1860/s3p1860 has 20 pin package type only.
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 2 table 7-3. S3C1840/c1850/c1860 functions description automatic reset by halt mode release when halt mode is released, the chip is reset after an oscillator stabilization interval of 9 ms. (fxx = 455 khz) output pin state retention function when the system enters halt mode, p3.0-p3.3, p2.0, and p2.2-p2.5 go low level in 24 pins. p3.0-p3.3, p2.0, and p2.2-p2.4 go low level in 20 pins. but the p2.0 is floating state in s3c1850/c1860. (note) auto-reset with oscillation on and with no change to the ip2.0 output pin, a reset is activated every 288 ms at fxx = 455 khz. osc. stabilization time cpu instructions are executed after oscillation stabilization time has elapsed. other functions carrier frequency generator. halt wake-up function. note : the s3c1850 has 24 pin package type only and s3c1860 has 20 pin package type only. reset the S3C1840/c1850 has three kinds of reset operations: ? por (power-on reset) ? auto-reset ? automatic reset by halt release the s3c1860 has three kinds of reset operations; ? osr (oscillation start and reset) ? auto-reset ? automatic reset by halt release power-on reset circuits 7 pf 1 m w 0.3 v dd 2.2 v v dd reset reset time figure 7-1. power-on reset circuits
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 3 auto-reset the auto-reset function resets the cpu every 131,072 oscillator cycles (288 ms at fxx = 455 khz). the auto-reset counter is cleared when a rising edge is detected at ip2.0, or by a halt or reset pulse. normal mode halt halt release signal ip2.12 = 1, non-active input pin f xx = 455 khz osc. stabilization time (9 ms) osc. circuit wait time (3-4 ms) x o osc. stabilization counter starts auto-reset counter chip restarts and auto-reset counter is incremented. chip holds it's internal status. upon entering halt mode, the auto-reset counter is cleared to zero. systerm reset occurs when the auto-reset counter overflows. the program restarts from 0f00hh overflow ip2.0 ip2.0 normal mode: after a reset, the program restart from 0f00h after one instruction in 0fxxh is executed.('f' is page number and 'xx' is the next instruction of halt instruction) chip restarts and the auto-reset counter is incremented (reset by internal por or osr) abnormal status v dd figure 7-2. auto-reset counter function note : the osr(oscillation start and reset) is not implemented for the S3C1840/c1850.
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 4 automatic reset by halt mode release this function resets the cpu by releasing halt mode. the cpu is reset to its initial operating status and program execution starts from the reset address. halt mode and automatic reset by halt release halt mode is used to reduce power consumption by stopping the oscillation and holding the internal state. halt mode can be entered by forcing ip2.12 to high level (remaining input pins are non-active). before entering halt mode, programmer should pre-set all key strobe output pins to active state even though halt mode causes some pins to remain active. for the 24 pins, p3.0-p3.3, p2.0, p2.2- p2.4, and p2.5 are sent low and for 20 pins, p3.0-p3.3, p2.0, p2.2-p2.4 are sent low, but the p2.0 is floating state in s3c1850/c1860 . . forcing any key input port to active state causes the clock oscillation logic to start system initialization. at this time, the system is reset after the oscillation stabilization time elapses. a system reset causes program execution to start from address 0f00h. normal mode: after a reset, the program restarts from 0f00h after one instruction in 0fxxh is executed.('f' is page number and 'xx' is the instruction immediately following the halt instruction.) halt release signal ip2.12 = 1, non-active input pin normal mode halt x o osc. circuit wait time (3-4 ms) osc. stabilization timer start osc. stabilization timer (9 ms) fxx = 455 khz) figure 7-3. reset timing diagram
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 5 halt mode programming the S3C1840/c1850/c1860 can enter halt mode by setting the ip2.12 pin to high level and forcing p0 and p1 input to a normal state. if ip 2.12 is high and any input is active, the chip cannot enter halt mode. therefore, the next instruction is executed, which must be a clear command for ip2.12. mov l,#5 keyolo clrb p2.(l) ; p2.5,4,3,2, ? low decs l cpne l,#1 jp keyolo clr a ; a cc . ? #0h out p3,@sl+a ; p3.0,1,2,3, ? low mov l,#0dh clrb p2.(l) ; select the p0 input in a,p0 incs a ; p0 input check jp .+2 jp keychk ; if any key pressed in p0, jump to keychk routine setb p2.(l) ; select the p1 input timea in a,p0 incs a ; p1 input check jp + 2 timeb jp keychk ; if any key pressed in p1, jump to keychk routine mov l,#0ch ; no key pressed setb p2.(l) ; halt mode ; when no key is pressed, the chip enters halt mode. pressing any key while in halt mode causes the chip to be initialized and restarted from the reset address. ; if any key is pressed between time a and time b, the following instruction is executed. mov l,#0ch ; these two instructions remove the condition of re-entering clrb p2,(l) ; halt mode.
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 6 reset reset and halt halt logic diagram ip2.12 4 internal halt 4 p0 p1 system reset internal por or osr (note) auto-reset counter internal halt ip 2.0 f osc clk 4 4 note: internal por is implemented for S3C1840/c1850 and osr is implemented for s3c1860. figure 7-4. reset reset and halt halt logic diagram
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 7 output pin description indicator led drive output to drive the indicator led, the programmer should use p2.1 of the S3C1840/c1850/c1860 (which have higher current drive capability than other pins) in order to retain the pre-programmed status during halt mode. be careful to turn on the led when a reset signal is generated. because a reset signal sends all of the internal and external output pins to low level, the programmer must set led output p2.1 to high state using a reset subroutine. p2.1 figure 7-5. led drive output circuit strobe output option to active the optional strobe output function for tv and vcr remocon applications, the programmer must use the option selection strobe output pin (p2.6). this pin has lower current drive capability than other pins and retain the pre-programmed status while in halt mode. be careful to turn on the option strobe output pin when a reset signal is generated. because the reset sends all internal and external output pins to low level, the option strobe output pin should always be non-active state (h-z). the pin should be active only when you are checking option status to reduce current consumption. table 7-4. strobe output option pin usage key output led drive option selection p3.0-p3.3, p2.2-p2.5 00 x x p2.1 0 00 0 p2.6 0 0 00 note: x = not allowed 0 = good 00 = better
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 8 output pin circuit type p2.1, p2.6 p2.6: for option pin or key-out p2.1: for led drive pin or key-out data x 0 0 x 1 h-z halt data port data halt p3.0-p3.3, p2.2-p2.5 low output retention function in halt mode is used for key strobe output only 0 0 0 0 1 h-z 0 x 0 halt data port figure 7-6. output pin circuits
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 9 soft ware delay routine to obtain a constant time value, the S3C1840/c1850/c1860 use a software delay routine (there is not an internal timer interrupt). one instruction cycle is six oscillator clocks. using a ceramic resonator with a constant frequency, you can calculate the time delay as follows: t = 6/fxx number of instructions where t: elapsed time and fxx: system clock. programming tip to program a 1-ms delay: 1 ms = 6/455 khz x n, where fxx = 455 khz therefore, n = 75.8 = 76 instructions dly1ms clr a adds a,#0bh ; two instructions dly mov h,#0 ; dummy instruction mov h,#0 ; dummy instruction mov h,#0 ; dummy instruction mov h,#0 ; dummy instruction decs a jp dly ; dly loop: 6 instructions ;2 + (acc + 1) x instructions in loop = 2 + (11 + 1) x 6 = 74 clr a clr a ; two instructions. ; total number of instructions for dly1ms is 76. note in order to lengthen the delay time, you can use an arithmetic instruction combination of l register and accumulator. the l register causes the address lower pointer to access ram space and the output port pointer to control the p2 (individual/serial output) port status. ? ram manipulation instruction: ram address pointer. mov a,@hl cpne @hl,a adds a,@hl setb @hl.b ? p2 output control instruction: p2 pointer. setb p2.(l) clrb p2.(l)
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 10 programming guidelines when programming S3C1840/c1850/c1860 microcontroller, please follow the guidelines presented in this subsection. pcb artwork for remote control applications, turning the i.r.led on and off may cause variations in transmission current ranging from a few hundred m a to a few hundred ma. this current variation generates overshoot and undershoot noise on the power line, causing a system malfunction. remocon signal v dd to reduce noise and to stabilize the chip's operation, we recommend that the application designer reduce overshooting of the i.r.led drive current and design pcb for the remote controller as follows: (the noise level should be limited to around 0.5 v p-p , where v p-p is the peak-to-peak voltage) ? oscillation circuit should be located as near as possible to the chip. ? pcb pattern for v dd /v ss should be as wide and short as possible. ? i.r.led drive tr and i.r.led should be located as far as possible from the chip. ? power supply battery and power capacitor should be located as ne ar as possible to the chip. ? the ground pattern of the test pin (ground of i.r.led drive tr) and v ss pin should be separated and connected directly with the battery terminal. ? the ceramic capacitor (0.1uf or 0.01uf) and power capacitor(over 47uf) is recommended to use noise filter.
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 11 c2 c3 c1=47uf gnd v dd v ss x in x out v dd p2.0 test gnd v dd c1=47uf c4=0.1uf c2 c3 v ss x in x out v dd p2.0 test recommended artwork for s3c1850/c1860 unacceptable artwork for s3c1850/c1860
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 12 smds when a breakpoint or single-step instruction is executed in area of page and jp or call instruction, the jp or call may jump to the wrong address, we therefore recommend using a jpl or call instruction (instead of page and jp or page and call) to avoid this problems. note that jp and call are 2-byte instructions. programming guidelines for reset subroutine 1. we recommend that you initialize a h register to either "0" or "4" 2. do not write the instructions calll (page + call) or jpl (page + jp) to the reset address 0f00h. in other words, do not use a page instruction at 0f00h. 3. turn off the led output pin. 4. to reduce current consumption, do not set the option output pin to active state. 5. pre-set the remocon carrier frequency (to fxx/12, fxx/8, and so on) before remocon signal transmission. 6. because the program is initialized by an auto-reset or halt mode release, even in normal operating state, do not pre-set all ram data. if necessary, pre-set only the ram area you need. 7. be careful to control output pin status because some pins are automatically changed to active state. 8. to enter halt mode, the internal port, ip2.12, should be set to high level and all of the input pins should be set to normal state. 9. to release halt mode, an active level signal is supplied to input pins. if pulse width is less than 9 ms at fxx = 455 khz, nothing happens and program re-enters halt mode. that is, the external circuit should maintain the input pulse over a 9-ms interval in order to release halt mode. after halt mode is released, the hardware is reset. the hardware reset sends all internal and external output pins low (except p2.0 in s3c1850/c1860) and clears the stack to zero. however, h,l and a registers retain their previous status. 10. if a rising edge is not generated at ip2.0, reset signal occurs every 288 ms at fxx = 455 khz. to prevent an auto-reset, ip2.0 should be forced low and then high at regular intervals (within 288 ms at fxx = 455 khz).
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 13 S3C1840 application circuit example d1 v dd p2.0/ rem test p2.1 p2.2 p2.3 p2.4 p2.5 p3.0 p3.1 p3.2 p3.3 v ss xi xo p2.6 p0.0 p0.1 p0.2 p0.3 p1.0 p1.1 p1.2 p1.3 samsung S3C1840-xx c2 c1 c4 c3 c6 c5 c8 c7 c2 c3 k8 k24 k16 k40 k32 k56 k48 k9 k1 k25 k17 k41 k33 k57 k49 k10 k2 k26 k18 k42 k34 k58 k50 k11 k3 k27 k19 k43 k35 k59 k51 k12 k4 k28 k20 k44 k36 k60 k52 k13 k5 k29 k21 k45 k37 k61 k53 k14 k6 k30 k22 k46 k38 k62 k54 k15 k7 k31 k23 k47 k39 k63 k55 k0 r2 d2 r1 + - c4 c1 +3 v v dd r1: 1-0.45 w r2: 100 w c1: 4.7 m f/6.3 v c2, c3: 100 pf c4: 0.1 m f d1: i.r.led d2: indicator led resonator: 455 khz k c or figure 7-7. S3C1840 applicatrion circuit example
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 14 s3c1850 application circuit example d1 v dd p2.0/ rem test p2.1 p2.2 p2.3 p2.4 p2.5 p3.0 p3.1 p3.2 p3.3 v ss xi xo p2.6 p0.0 p0.1 p0.2 p0.3 p1.0 p1.1 p1.2 p1.3 samsung s3c1850-xx c2 c1 c4 c3 c6 c5 c8 c7 c2 c3 k8 k24 k16 k40 k32 k56 k48 k9 k1 k25 k17 k41 k33 k57 k49 k10 k2 k26 k18 k42 k34 k58 k50 k11 k3 k27 k19 k43 k35 k59 k51 k12 k4 k28 k20 k44 k36 k60 k52 k13 k5 k29 k21 k45 k37 k61 k53 k14 k6 k30 k22 k46 k38 k62 k54 k15 k7 k31 k23 k47 k39 k63 k55 k0 r d2 + - c4 c1 +3 v v dd r: 100 w c1: 4.7 m f/6.3 v c2,c3: 100 pf c4: 0.1 m f d1: i.r.led d2: indicator led resonator: 455 khz k c or figure 7-8. s3c1850 application circuit example
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 15 s3c1860 application circuit example d1 v dd p2.0/ rem test p2.1 p2.2 p2.3 p2.4 p3.0 p3.1 p3.2 v ss xi xo p0.0 p0.1 p0.2 p0.3 p1.0 p1.1 p3.3 samsung s3c1860-xx c2 c3 k7 k21 k14 k35 k28 k8 k1 k22 k15 k36 k28 k9 k2 k23 k16 k37 k30 k10 k3 k24 k17 k38 k31 k11 k4 k25 k18 k39 k32 k12 k5 k26 k19 k40 k33 k13 k6 k27 k20 k41 k34 k0 r2 d2 + - c4 c1 +3 v v dd r1: 1-5 w r2 : 100 w c1: 47 m f/6.3 v c2,c3: 100 pf c4: 0.1 m f d1: i.r.led d2: indicator led r1 k figure 7-9. s3c1860 application circuit example
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 16 program flowchart (this program is only apply to S3C1840) one key input? reset debounce time all key strobe output pins are non-active transmit two waveforms transmit repeat waveforms only one key strobe pin is active debounce time = 0? data & custom code generator continous key? main yes no yes no no yes double key & no key reset main keyscan datcus signal tx. no yes any key input? all key strobe output pins are active halt start figure 7-10. program flowchart 1
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 17 S3C1840/c1850 keyscan function description this program has an 8 x 9 key matrix, which consists of input p0 and p1 and output p2 and p3. because pull-up resistors are connected, the normal state for all input pins is high level. the operating method for the keyscan function is as follows: ? all output pins remain active state ( = low). ? if key is pressed, set all output pins to non-active state and rotate the pins to set only a pin to active state during debounce time. ? if key is pressed more than one or if no key is pressed, go to reset label. ? if a new key is pressed, reset debounce time, continuous flag, and key-in flag. ram assignment o_inp0 n_inp0 o_inp1 n_inp1 o_outp i_twice n_outp debocnt conkey kflg 05h 09h h register selects #0 01h hl 00h o_inp0: the old value of p0 n_inp0: the new value of p0 o_inp1: the old value of p 1 n_inp1: the new value of p1 o_outp: the old value of output port n_outp: the new value of output port i_twice: double number increment debocnt: debounce time conkey: continuous key flag kflg: key input flag
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 18 program flowchart (this program is only apply to S3C1840) 518kscan o_inp0, o_inp1, o_outp #0fh debocnt, conkey #0 p2.1 & 2.6 high port3, p2.2-p2.5 low port 0 = #0fh port 1 = #0fh n_outp.2 = #1 a reset ; close indicator led & option pin ; active strobe output pins ; initial variable ; check port 0 input no no ; check port1 input ; halt mode & halt mode release ; h register selects #0 ; non-active strobe output pins ; only one output pin is low level ; parall main strobe: serial: no yes p2.5 high port 3 low h #0 p2.2-p2.5 low port3, p2.2-p2.5 high p2.12 high p2.12 low n_outp, kflg #0, i_twice #1 yes yes figure 7-11. program flowchart 2
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 19 a reset port 0 = #0fh n_inp0 port 0 n_inp1 #0fh l n_inp0 port 1 = #0fh a a + #1 overflow? a a - #1 n_inp0 a n_outp o_outp n_outp = o_inp0 n_inp0 o_inp0 n_inp0 = o_inp0 n_inp1 o_inp1 n_inp1 = o_inp1 debocnt #2 conkey #0 kflg #1 port 1 = #0fh n_inp0 #0fh n_inp1 port 1 l n_inp1 a a + #1 overflow? a a - #1 n_inp1 a a normal reset key in: port 0: ; double key dbcomp: ;key input setting setkey: ;new key & debounce time setting ;compare old data to new data ; double key ; no key port 1: ; check the end of debounce time incs n_outp a n_outp = #8 kflg = #1 p3.3 high decs debocnt debocnt = #0 ret reset main strobe normal: no key yes yes no yes no yes no no no yes no yes no no yes no yes no no yes keycheck keycheck yes yes fstkey: figure 7-12. program flowchart 3
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 20 S3C1840/c1850 keycheck subroutine l= #07h no no no l = #0dh keychek a #0fh l = #0eh a a + #1 l = #0bh a a + #2 a a + #3 a a + #4 ret no yes yes yes figure 7-13. S3C1840/c1850 keycheck subroutine
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 21 ;********************************************* org 0f00h ;********************************************* ; if reset occurs, pa register is immediately initialized to #0fh reset mov l,#1 ; close indicator led setb p2.(l) ; mov l,#6 ; non-select p2.6 setb p2.(l) ; prtclr clr a ; out p3,@sl + a ; low all the output ports mov l,#5 ; (except p2.0, p2.1, p2.6) clrb p2.(l) ; decs l ; cpne l,#1 ; jp .-3 ; ;;; initial all of the variables -------------------------------------------------- ;;; ? input ports are connected with pull-up resistor ;;; ? therefore, normal state ? high mov h,#0 ; h register selects file #0 mov l,#o_inp0 ; port0 is #0fh mov @hl+,#0fh mov l, #o_inp1 ; port1 is #0fh mov @hl +,#0fh mov l, #o_outp ; the strobe out is #0fh mov @hl+,#0fh mov l,#debocnt ; debounce count is #0 mov @hl+,#0 mov l,#conkey ; continuous key is #0 mov @hl+,#0 ;;; check each input port (=key input) ------------------------------------ mov l,#0dh ; check port0 clrb p2.(l) ; in a,p0 ; mov l,a ; cpne l,#0fh ; jp delayp0 ; mov l,#0dh ; check port1 setb p2.(l) ; in a,p0 ; mov l,a ; cpne l,#0fh ; jp j_main ; ;;; halt mode, after halt mode release, go to reset ------------------ mov l,#0ch setb p2.(l) ; halt mode clrb p2.(l) ; halt mode release jp reset
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 22 prtset clr a ; adds a,#0fh ; high all the output ports out p3,@sl+a ; (p3, p2.2-p2.5) mov l,#5 ; setb p2.(l) ; decs l ; cpne l, #1 ; if p2.0 is high, data tx. jp .- 3 ; and auto reset counter clear ret delayp0 mov h #0 ; for the match of delay time mov h #0 ; mov h #0 ; mov h #0 ; mov h #0 ; mov h #0 ; j_main jpl main ; ; ;********************************************* org 0000h jpl reset ;********************************************* main mov h,#0 ; h regisster selects file #0 ; useful when continous pulse tx. ; calll prtset ; high all the output ports ;;; initial useful variable in main routine ------------------------------------ mov l,#n_outp ; n_outp ? #0 mov @hl+,#0 ; mov l,#1_twice ; i_twice (double increment) ? #1 mov @hl+,#1 ; mov l,#kflg ; kflg ? #0 (input key flag) mov @hl+,#0 ; ;; select output pin by one and one --------------------------------- strobe mov l,#n_outp cpbt @hl.2 ; if n_outp.2 is set, go to parall (parallel port) jp parall ; otherwise, go to serial (serial port) serial mov l,@hl ; incs l ; setb p2.(l) ; low p2.2-p2.5 incs l ; clrb p2.(l) ; jpl keyin parall mov l,#5 ; high p2.5 setb p2.(l) ;
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 23 ;;;********************************************* ;;; a ? #0h ;;; a ? a-1_twice ;;; output p3 ;;; i_twice ? i_twice + i_twice ;;; ;********************************************* clr a ; a ? #0fh adds a, #0fh ; mov l, #1_twice ; xch @hl,a ; a ? a-i_twice subs a,@hl ; out p3,@sl+a ; low port3 subs a,@hl ; mov @hl,a ; recover i_twice adds a,@hl ; movz @hl,a ; i_twice ? i_twice + i_twice jpl keyin ;;;********************************************* ;; check double key at each port ;; if a key pressed, do adds instruction ;; otherwise, induce overflow occurrence ;;;********************************************* keychek clr a adds a,#0fh ; a ? #0fh cpne l,#0eh jp .+2 adds a,#1 ; a ? #0 cpne l,#0dh jp .+2 adds a,#2 ; a ? #1 cpne l,#0bh jp .+2 adds a,#3 ; a ? #2 cpne l,#7 jp .+2 adds a,#4 ; a ? #3 ret ; ; ; ********************************************* org 0100h jpl reset ; ********************************************* keyin mov l,#0dh clrb p2.(l) ;;; select port0 --------------------------------- in a, p0 mov l,a cpne l,#0fh ; is key pressed in port0 ? jp port0 jp port1
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 24 port0 mov l,#n_inp0 ; setting at n_inp0 mov @hl,a ; mov l,#odh ; setb p2.(l) ; in a,p0 ; mov l,a ; cpne l,#0fh ; jp dbkey ; if also port1 input a key, ; it is double key mov l,#n_inp1 ; only n_inp0 input mov @hl+,#0fh ; but n_in p1 is set to #0fh mov l,#n_inp0 ; mov l,@hl ; calll keychek ; adds a,#1 ; jp dbkey ; if overflow occurs, it is double key decs a ; because input value ranges mov l,#n_inp0 ; from #0 to #3 movz @hl,a ; n_inp0 ? a jpl dbcomp ;;; select port1 --------------------------------- port1 mov l,#0dh setb p2.(l) in a,p0 mov l,a cpne l,#0fh ; is key pressed in port 1? jp .+3 jpl normal ; no key, go to normal mov l,#n_inp0 ; setting n_inp0 to #0fh mov @hl+,#0fh ; only n_inp1 input mov l,#n_inp1 ; mov @hl,a ; mov l,a ; l ? n_inp1 calll keychek adds a,#1 ; if overflow occurs, go to double key jp dbkey ; decs a ; because input value ranges from #0 to #3 m ov l,#n_inp1 ; n_inp1 ? a movz @hl,a jpl dbcomp ;;; if double key occurs, go to reset --------------------------------- dbkey jpl reset ; ;
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 25 ; ********************************************* org 0200h jpl reset ; ********************************************* ;;; compare for the recognition of a new key---------------------- dbcomp mov h,#n_outp ; compare n_outp to o_outp mov a,@hl mov l,#o_outp xch @hl,a cpne @hl,a jp fstkey mov l,#n_inp0 ; compare n_inp0 to o_inp 0 mov a,@hl mov l,#o_inp0 xch @hl,a cpne @hl,a jp fstdly mov l,#n_inp1 ; compare n_inp1 to o_inp1 mov a,@hl mov l,#o_inp1 xch @hl,a cpne @hl,a jp fstkey jp setkey fstdly mov h,#0 ; for match of delay time mov h,#0 mov h,#0 mov h,#0 mov h,#0 ;;; when new key input ---------------------------- fstkey mov l,#debocnt ; debocnt ? #2 mov @hl+,#2 mov l,#conkey ; conkey ? #0 mov @hl+,#0 setkey mov l,#kflg ; kflg ? #1 mov @hl+,#1
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 26 ; ********************************************* ;;; increase n_outp ;;; check n_outp is equal to #8 ;;; check no key (= debocnt) ; ********************************************* normal mov l,#n_outp ; increase n_outp incs a,@hl movz @hl,a adds a,#8 ; a ? #8 cpne @hl,a ; compare n_outp to a jp j_stro ; go to stroble label mov l,#kflg ; cpbt @hl.0 ; check key flag jp onkey jpl reset ; no key onkey clr a adds a,#0fh out p3,@sl + a ; set p ort3 to ?1? mov l,#debocnt ; decrease debocnt decs a,@hl xch @hl,a cpnz @hl ; compare debocnt to #0 jp j1_main jpl keyscan j1_main jpl main j_stro jpl strobe
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 27 S3C1840/c1850 code generation description this program generates data code and custom code. the custom code is determined according to diodes between input ports and output pin (p2.6). the data code is as follows: d0 d1 d2 d4 d5 d3 d6 d7 key1 key0 key33 key32 key31 key63 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 . . . . . . . . d0 d1 d2 d4 d5 d3 d6 d7 key1 key0 key33 key32 key31 key63 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 . . . . . . . . ram dat0 (d0-d3), dat1_0 (d4-d7) ram dat0 (d0-d3), dat1 (d4-d7) ram assignment cus0 cus1 cus2 cus3 dat0 dat2 dat1 dat3 dat1_0 dat3_0 45h 49h h register selects #4 41h hl 40h cus0; custom code (c0-c3) cus1: custom code (c4-c7) cus2: the complement of cus0 cus3: the complement of cus1 dat0: data code (d0-d3)] dat1: data code (d4-d7) : ? 32 key: 00000010, 63 key: 1111010 dat2: the complement of dat0 dat3: the complement of dat1 dat1_0 data code (d4-d7) : ? 32 key: 00000100, 63 key: 1111100 dat3_0 the complement of dat1_0
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 28 program flowchart 518code ; select option pin ; custom code production ; close option pin ; indicator led dat0 = #0fh dat1 <- #0 dat1_0 <- #0 dat_p0: carry ? dat_p1: r_shift: s_carry: a_outp: ; check the end of debounce time ret n y n y y h <- #4 p2.6 <- low p2.13 <- low produce cus0 & cus2 p2.6 <- high p2.13 <- high produce cus1 & cus3 p2.1 <- low dat0 <- o_inp0 dat1 <- #4 dat1_0 <- #2 dat0 <- o_inp1 l <- dat0 dat0 shifts three times to left incs dat1 & dat1_0 dat0 <- dat0+o_outp dat2 <- the complement of dat0 dat3 <- the complement of dat1 dat1_0 <- the complement of dat3_0 figure 7-14. program flowchart 4
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 29 ;********************************************* org 0300h jpl reset ;********************************************* ;;; select only a key ------------------------------------------------ keyscan mov h,#4 ;;; product custom code ------------------------------------------- mov l,#6 ; p2.6 ? low clrb p2.(l) ; check custom code mov l,#0dh ; clrb p2.(l) ; in a,p0 ; mov l,#cus2 ; cus2 is the complement of cus0 mov @hl,a ; noti a ; decs a ; mov l,#cus0 ; mov @hl,a ; mov l,#0dh setb p2.(l) ; cus3 is the complement of cus1 in a,p0 ; mov l,#cus3 ; mov @hl,a ; adds a,@hl ; noti a ; decs a ; mov l,#cus1 ; movz @hl,a ; mov l,#6 ; high p2.6 setb p2.(l) mov l,#1 ; the indicator led of a key input clrb p2.(l) ;;; product data code ------------------------------------------------- mov h,#0 mov l,#o_inp0 ; dat0 ? o_inp0 mov a,@hl mov h,#4 mov l,#dat0 movz @hl,a adds a,#0fh ; a ? #0fh cpne @hl,a ; does input key exist in port0? jp dat_p0
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 30 dat_p1 mov l,#dat1 ; input key exists in port1 mov @hl+,#04h ; dat1 ? dat1 + #4 mov l,#dat1_0 mov @hl+,#02h ; dat1_0 ? dat1_0 + #2 mov h,#0 ; dat0 ? o_inp1 mov l,#o_inp1 ; mov a,@hl ; mov h,#4 ; mov l,#dat0 ; movz @hl,a ; jpl r_shift ; dat_p0 mov l,#dat1 ; clear dat1 & dat1_0 mov @hl+,#0 mov l,#dat1_0 mov @hl+,#0 mov l,#dat0 mov h,#4 ; delay time mov h,#4 ; mov h,#4 ; mov h,#4 ; mov h,#4 ; jpl r_shift ; ; ;********************************************* org 0400h jpl reset ;********************************************* r_shift mov a,@hl ; dat0 shifts three times to the left adds a,@hl ; mov @hl,a ; adds a,@hl ; mov @hl,a ; adds a,@hl ; jp s_carry jp n_carry s_carry mov l,#dat1 ;if carry occurs, increase dat1 & dat1_0 xch @hl,a ; incs a ; xch @hl,a ; mov l,#dat1_0 ; xch @hl,a ; incs a ; xch @hl,a ; jp a_outp
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 31 n_carry mov h,#0 ; if carry doesn 't occur, delay time mov h,#0 ; mov h,#0 ; mov h,#0 ; mov h,#0 ; mov h,#0 ; mov h,#0 ; mov h,#0 ; a_outp mov h,#0 mov l, #o_outp ; dat0 ? dat0 + o_outp adds a,@hl ; mov h,#4 ; mov l,#dat0 mov @hl,a ; noti a decs a ; dat2 ? complement of dat0 mov l,#dat2 movz @hl,a mov l,#dat1 mov a,@hl noti a ; dat3 ? complement of dat1 decs a mov l,#dat3 movz @hl,a mov l,#dat1_0 mov a,@hl noti a decs a mov l,#dat3_0 ; dat3_0 ? complement of dat 1_0 mov @hl,a jpl tx
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 32 S3C1840/c1850 signal transmission description this program is for signal transmissions in samsung standard format. if one key is pressed, two frames are transmitted consecutively. the repeat pulse is transmitted until key-off. the frame interval is 60 ms. each frame consists of leader code, custom code, and data code: ? leader code (high level for 4.5 ms and low level for 4.5 ms) ? 12-bit custom code ? 8-bit data code transmission waveform 60 ms frame waveform leader code 4.5 ms 4.5 ms 60 ms 60 ms custom code (c0-c11) data code (d0-d7) data pulse 0.56 ms 1.125 ms data '0' 2.25 ms 0.56 ms data '1' figure 7-15. transmission waveforms ram assignment this part is the same as for keyscan and code generation.
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 33 S3C1840 program flowchart (this program is only apply to S3C1840) p2.9 & 2.10 low conkey + #0 518samtx cus4 #0 p2.0 high for 4.5 msec p2.0 low for 4.5 msec p2.0 high for .56 msec p2.0 low delay as many as low number output custom & data code debocnt #1 conkey #1 delay for 60 msec ; select carrier frequency ; c8 #0 main delay for 60 msec ; repeat waveform transmission ; until key off yes ; repeat one more time no figure 7-16. S3C1840 program flowchart 5
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 34 ;********************************************* org 0500h jpl reset ;********************************************* tx mov l,#9 ; select farrier frequency clrb p2.(l) ; 37.9 khz, 1/3 duty mov l,#0ah ; clear p2.9 & 2.10 clrb p2.(l) sigout mov l,#cus4 ; custom code (c8-c11) ? #0 mob @hl+,#0 ; if device is ks51910 , c8 ? #1 ;;; output head pulse -------------------------------------------------- mov l,#0 ; high for delay time 4.5 msec setb p2.(l) calll d4_5 mov l,#0 clrb p2.(l) ; low for delay time 4.5 msec calll d4_5d ;;; output custom code (c0-c11) & data code (d0-d7) mov l,#cus0 ; custom code (c0-c3) calll datgen mov l,#cus1 ; custom code (c4-c7) calll datgen mov l,#cus4 ; custom code (c8-c11) calll datgen mov l,#dat0 ; data code (d0-d3) calll datgen mov l,#dat1_0 ; data code (d4-d7) calll datgen mov l,#1 decs l jp .-1 mov l,#0 ; eob (end of bit) setb p2.(l) ; high for .56msec calll d_560f mov l,#0 clrb p2.(l) jpl lowchek
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 35 ;********************************************* org 0600h jpl reset ;********************************************* ;;; check low code of custom code & data code -------------------------------- lowchek mov l,#cus0 ; custom code (c0-c3) call lchek mov l,#cus1 ; custom code (c4-c7) call lchek mov l,#cus4 ; custom code (c8-c11) call l chek mov l,#dat0 ; data code (d0-d3) call lchek mov l,#dat1_01 ; the maximum value of upper bit is #3 mov a,l ; data code (d4-d7) call lchek_1 ; check from the second bit ;== notice =========================================================== ; if value of dat1_0 is greater than #3, programmer must change instruction ; calllchek_1 to other instruction such as callcheck_2 or call ; lchek. and you must check the fram interval (= 60 msec) ;=================================================================== ;;; re-setting debounce count to #1------------------------------------- setdbt mov h,#0 mov l,#debocnt ; debocnt ? #1 mov @hl+,#1 ;--------------------------------------------------------------------------------- ;;; if conkey flag isn?t ?0?, transmit repeat pulse ;;; otherwise, after setting, transmit again (two frames) ;--------------------------------------------------------------------------------- conchek mov h,#0 mov l,#conkey ; conkey == #0? cpnz @hl ; if conke y is #0, conkey ? #1 jp lj_main ; transmit frame again mov @hl+,#1 calll d4_5d ; time is 60 msec per frame calll d2_25 calll d1_125 mov l,#0ch mov h,#4 mov h,#4 decs l jp .-3 jpl sigout
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 36 ;;; output repeat pulse ---------------------------------------------------------- lj_main call d1_125 jpl main ;;; output delay time as many as low numbers ---------------------------- lchek mov a,l cpbt @hl,3 ; if @hl.3 is low, call d2_25d. jp lchek_2 calll d2_25d lchek_2 mov l,a cpbt @hl.2 ; if @hl.2 is low, call d2_25d. jp lchek_1 calll d2_25d lchek_1 mov l,a cpbt @hl.1 ; if @hl.1 is low, call d2_25d. jp lchek_0 calll d2_25d lchek_0 mov l,a cpbt @hl.0 ; if @hl. 0 is low, call d2_25d. jp lchek_r calll d2_25d lchek_r ret ; ; ; ; ; ;********************************************* org 0700h jpl reset ;********************************************* ;; custom code & data code generation ------------------------------------- datgen mov a,l call d_560 ; high for .56 msec c pbt @hl.0 ; if @hl.0 is high, low for 2.25 msec. call d2_25 ; otherwise, low for 1.125 msec. call d1_125
S3C1840/c1850/c1860/p1860 remote contro l tx. application note 7 - 37 call d_560 ; high for .56 msec cpbt @hl.1 ; if @hl.1 is high, low for 2.25 msec. call d2_25 ; otherwise, low for 1.125 msec. call d1_125 call d_560 ; high for .56 msec cpbt @hl.2 ; if @hl.2 is high, low for 2.25 msec. call d2_25 ; otherwise, low for 1.125 msec. call d1_125 call d_560 ; high for .56 msec cpbt @hl.3 ; if @hl.3 is high, low for 2.25 msec. call d2_25 ; otherwise, low for 1.125 msec. call d1_125d ret ;;; delay time subroutine by programming ----------------------------------- d_560 mov l,#0 setb p2,(l) ; mov l,#0ch mov h,#4 decs l jp .-2 mov h,#4 ; mov l,#0 clrb p2.(l) mov l,a ret d4_5d mov l,#02h ; delay time 4.5 msec jp .+2 d4_5 mov l,#06h decs l jp -1 mov l,#05h clr a adds a,#0bh mov h,#4 d_a decs a jp .-2 decs l jp .-6
remote control tx. application note s3c 1840/c1850/c1860/p1860 7 - 38 d2_25d mov l,#0eh jp .+2 d2_25 mov l,#0fh mov h,#4 decs l jp .-2 d1_125 mov l,#0ah jp .+6 d1_125d mov l,#08h jp .+4 d_560f mov l ,#0bh ; delay time .56 msec (for eob) mov h,#4 mov h,#4 decs l jp .-2 ret ; ; org 0800h jpl reset org 0900h jpl reset org oaooh jpl reset org obooh jpl reset org ocooh jpl reset org odooh jpl reset org oeooh jpl reset ; ;******************* the end of S3C1840 samsung format tx. **************************

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